8 - year experience as a DFT Engineer, proficient in the full - process design of DFT, and familiar with various chip architectures. <br> - With rich project management experience, successfully led multiple complex chip DFT projects. <br> - Good at communication and collaboration, able to work efficiently with cross - departmental teams to solve technical problems. <br> - Continuously pay attention to cutting - edge industry technologies, such as the application of AI in DFT, and continuously improve self - competitiveness.
Education Experience
Xidian University
211 ProjectDouble First - Class
Electronic Information Engineering
Bachelor's Degree
2015 . 092019 . 06
Systematically studied professional courses such as Digital Circuits, Analog Circuits, Signals and Systems, with excellent grades and ranking in the top 10% of the major. <br> - Participated in the Electronic Design Competition, responsible for circuit design and debugging, and won the provincial second prize.
Work Experience
Huawei Technologies Co., Ltd.
Fortune 500Leading in Communication Technology
Chip R & D Department
DFT Engineer
DFT DesignATPGTest Optimization
2019 . 072022 . 06
Shenzhen
Responsible for the testability design (DFT) of chips, including scan chain insertion, MBIST design, ATPG, etc. Successfully completed the DFT design of [X] chips, increasing the chip test coverage to [X]%.
Closely cooperated with the design team to optimize the DFT scheme, reducing the testing time by [X]% and the testing cost by [X]%.
Compiled DFT - related documents, such as DFT Specification and Test Plan, to provide clear guidance for the testing team.
Tencent Technology (Shenzhen) Co., Ltd.
Internet GiantInnovative Technology
Chip R & D Center
Senior DFT Engineer
SOC DFTMixed - Signal TestingMass Production Support
2022 . 072024 . 06
Shenzhen
Led the DFT architecture design of complex SOC chips, led the team to complete [X] projects, and shortened the project cycle by [X]%.
Introduced advanced DFT technologies, such as mixed - signal testing and low - power testing, to enhance the comprehensiveness and efficiency of chip testing.
Communicated and coordinated with external testing manufacturers to solve technical problems in the testing process and ensure the smooth mass production of chips.
Project Experience
DFT Design of High - Performance Processor Chip
DFT Engineer
Huawei Technologies Co., Ltd.
2020 . 012021 . 12
[Chip Name] DFT Design Project
This project is for a high - performance processor chip, responsible for the overall DFT scheme planning.
Inserted scan chains, optimized the scan chain structure, and made the scan chain coverage reach [X]%.
Designed the MBIST scheme, realized the automation of memory testing, and reduced the testing time by [X]%.
Generated ATPG test vectors, with the test vector compression rate reaching [X]%, effectively reducing the test data volume.
SOC Chip DFT Project
Senior DFT Engineer
Tencent Technology (Shenzhen) Co., Ltd.
2023 . 012024 . 06
[Chip Name] SOC Chip DFT Project
As the project leader, planned the DFT strategy and coordinated the design, verification, and testing teams.
Designed the DFT architecture, including modules such as logic scan, Memory BIST, and mixed - signal testing.
Optimized the testing process, and through technologies such as parallel testing, shortened the testing time from [X] hours to [X] hours.
The project was successfully mass - produced, with the yield rate increased by [X]%, and won the company's "Excellent Project Award".
Honorary Awards
Company Excellent Project Award
Departmental Technological Innovation Award
Other Information
DFT Technology Research:
Published [X] technical papers in the DFT field, such as [Paper Name], proposing innovative DFT optimization methods.
Participated in industry DFT technology seminars, shared experiences, and exchanged the latest technology trends with peers.