Digital Backend Engineer简历模板
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Peter Xiong
13800000000
zhangwei@example.com
Shanghai
30
Male
Digital Backend Engineer
Employed
Shanghai
30k-40kEducation Experience
Xidian University - Master211Double First-Class
2015.092018.06
Electronic Information Engineering
- Systematically studied professional courses such as digital circuit design and integrated circuit manufacturing process, with excellent grades, GPA 3.8 (out of 4.0).
- Participated in the school's integrated circuit design laboratory project, familiar with the use of EDA tools such as Cadence, and has a solid theoretical foundation and practical ability.
Work Experience
Hisilicon Semiconductor Co., Ltd. - Chip Design DepartmentIndustry LeaderTechnological Innovation
2018.072021.12
Digital Backend EngineerChip DesignBackend OptimizationSynopsys Tools
Shanghai
- Responsible for the backend design of [Company Product Name] chip, including the whole process of floorplan, clock tree synthesis (CTS), routing, etc.
- Using Synopsys toolchain, optimized chip area, power consumption and performance (PPA), reducing chip area by 15%, power consumption by 10%, and main frequency by 20%.
- Closely collaborated with the front-end design team to solve timing closure problems, and successfully taped out 3 chips with a yield rate of over 95%.
MediaTek (China) Investment Co., Ltd. - Digital Chip DivisionInternationally Renowned5G Chip
2022.012024.06
Senior Digital Backend EngineerTeam ManagementLow-Power DesignTiming Optimization
Shanghai
- Led the backend design of [Customer-Customized Chip Project Name], and led a 3-person team to complete the delivery from RTL to GDSII.
- Introduced advanced low-power design technologies (such as multi-threshold voltage, gated clock), reducing chip dynamic power consumption by 30% and static power consumption by 25%.
- Optimized the timing constraint file (SDC), solved complex cross-clock domain (CDC) problems, and the project was delivered 2 weeks ahead of schedule with a customer satisfaction of 100%.
Project Experience
5G Communication Chip Backend Design - Backend Design Engineer
2019.032020.10
Hisilicon Semiconductor Co., Ltd.
- The project is [5G Communication Chip Project Name], aiming to achieve high-speed data processing and low-power transmission.
- Responsible for backend physical design, by optimizing the power network (Power Network), reducing IR Drop by 20% and increasing EM (Electromigration) margin by 30%.
- Using formal verification (Formal Verification) to ensure logical consistency. Finally, in the 5G base station test, the chip's data transmission rate reached 1Gbps, and the power consumption was 15% lower than similar products.
Artificial Intelligence Chip Backend Development - Backend Optimization Leader
2022.052023.12
MediaTek (China) Investment Co., Ltd.
- [Artificial Intelligence Chip Project Name] aims to provide efficient AI computing power.
- Responsible for backend timing analysis and optimization. For the AI accelerator module, adopted asynchronous clock domain (Async CDC) design to improve data processing parallelism.
- Optimized the use of Memory Compiler, increasing the on-chip storage bandwidth by 40%. In the AI benchmark test, the chip's performance reached [specific value] TOPS/W, leading the industry.
Personal Summary
- 8 years of experience as a digital backend engineer, proficient in the full toolchain of Synopsys and Cadence, and successfully taped out 8 chips.
- Good at PPA optimization, with complex design capabilities such as low power consumption and high-speed interfaces, and rich team management experience.
- Continuously paying attention to industry frontiers (such as Chiplet, advanced packaging), with the ability of rapid learning and technological innovation.
Honor Awards
Company-level Excellent Project Award ([5G Chip Project Name])
Departmental Technological Innovation Award (Low-Power Design Technology)
Other Information
Chiplet Technology Research:
- Learned and practiced the Chiplet design process, familiar with interface standards such as UCIe.
- Participated in the company's internal Chiplet pre-research project, responsible for the backend design of the physical interface (PHY), and verified the timing and power consumption optimization methods for data transmission between Chiplets.
